Learn about the UART module’s functionality, its significance in embedded systems, and how it facilitates serial communication between devices.
A Universal Asynchronous Receiver-Transmitter (UART) serves as a critical hardware interface for asynchronous serial communication between digital devices. Its fundamental role is to transform parallel data from a computer or microcontroller into a serial bit stream for transmission and then reverse this process at the receiving end. This conversion hinges on precise timing coordination without relying on a shared clock signal between communicating devices. Instead, UART employs start and stop bits framing each data packet to maintain synchronization despite the asynchronous nature of the link.
The inception of UART technology traces back to early telegraphy equipment and teletypewriters where variable-length pulses and mechanical switching devices were utilized for character transmission. The first true UART was designed by Gordon Bell at Digital Equipment Corporation (DEC) for the PDP series beginning with the PDP-1. This design innovated by incorporating sampling techniques that digitized incoming signals more reliably than previous analog timing devices that used manually adjusted potentiometers.
Western Digital's WD1402A chip circa 1971 marked one of the earliest widely available single-chip UARTs, representing a medium-scale integrated circuit breakthrough. The National Semiconductor 8250 series emerged in the 1980s, becoming synonymous with IBM PC serial communications. By the 1990s, improvements such as on-chip FIFOs—exemplified by the National Semiconductor 16550 with its 16-byte FIFO buffer—enabled higher transmission speed without data loss and without requiring such frequent attention from the computer.
Distinct device names across manufacturers illustrate variations: Intel’s 8251 USART introduced in 1979 combined synchronous capabilities; MOS Technology’s 6551 was branded as an Asynchronous Communications Interface Adapter (ACIA); Motorola introduced Serial Communications Interfaces around 1975; Zilog produced Serial Communication Controllers (SCCs). Today, many UART functions are embedded directly within microcontrollers or processors.
A typical UART module integrates several components:
- A clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period.
- Input and output shift registers, along with the transmit/receive or FIFO buffers.
- Transmit/receive control and read/write control logic.
The electrical signaling levels handled by UART logic typically require external driver circuits adapting voltage levels—commonly RS-232, RS-485, or raw TTL levels suited for short-range debugging links.
UART communication modes include simplex (one-way), half-duplex (alternating directions), and full duplex (simultaneous transmission and reception). Achieving reliable communication mandates matching configurations on both ends regarding voltage levels (e.g., both operating at 3V–3V), baud rate, parity settings, number of data bits, stop bits, and flow control mechanisms.
Each UART frame consists of these sequential elements:
- An idle state held at logic high (\( \text{logic }\, 1 \)) indicates no transmission activity.
- A single start bit marked by a transition from high to low (\( \text{logic }\, 0 \)) signals the beginning of a character frame.
- Data bits follow next; commonly eight bits are used but configurations can vary between five and nine bits depending on the code set employed.
- An optional parity bit provides rudimentary error detection by verifying whether the count of set bits is even or odd.
- One or two stop bits return the line to the idle state (\( \text{logic }\, 1 \)), delineating frame termination.
This arrangement guarantees at least two signal transitions between successive characters—start low then stop high—to aid receiver synchronization.
In standard settings such as "8-N-1"—eight data bits, no parity, one stop bit—the protocol efficiency computes as \( \frac{8}{10} = 80\% \). Comparatively, Ethernet achieves higher efficiencies up to approximately 95% with standard frames (1500 bytes) or nearly 99% using jumbo frames (9000 bytes). However, due to Ethernet's protocol overhead and minimum payload size of 42 bytes, if small messages of one or a few bytes are to be sent, Ethernet's protocol efficiency drops much lower than the UART's 8N1 constant efficiency of 80%.
Baud rate defines transmission speed in bits per second. Commonly supported rates include 9600, 19200, 38400, 57600, and 115200 bps, with some UART modules capable of several megabits per second speeds.
Synchronization demands tight baud rate matching between transmitter and receiver. Deviations beyond roughly ±2% risk corrupting data integrity through misaligned sampling points; tolerances up to about ±5–10% represent upper limits before errors become pervasive.
At 9600 bps, each transmitted bit spans roughly 104 microseconds, necessitating accurate timing circuits within both devices. To enhance robustness against small clock discrepancies, many UART receivers implement oversampling techniques—for example, sampling each bit approximately sixteen times—to locate optimal sampling points near each bit's center.
Error handling in UART protocols relies primarily on parity checking supplemented by framing error detection:
A configured parity bit flags whether an odd or even number of set bits have been received; mismatches trigger parity error indicators alerting higher-level software layers.
Framing errors occur if expected stop bits are not detected correctly—such as when line voltage remains low when it should have gone high—suggesting loss of byte boundary alignment during reception.
Buffer overruns arise when a new byte arrives before the previous one was read from the receive buffer; hardware flags overrun events so software can react accordingly.
Break conditions manifest when the line remains continuously low longer than an entire character frame duration without any stop bit—a feature sometimes leveraged as an out-of-band signaling mechanism indicating special states like resets or mode changes.
Flow control mitigates buffer overflow risks during fast transmissions or when connecting devices with mismatched processing capabilities:
Hardware flow control employs dedicated RTS (Request to Send) and CTS (Clear to Send) lines allowing receivers to signal transmitters dynamically regarding their readiness status. This handshaking prevents transmission during receiver congestion without modifying transmitted data frames themselves.
Software flow control uses special characters embedded within the data stream—typically XON/XOFF—to pause/resume transmission sequences. While avoiding extra wiring complexity, it complicates protocol parsing since these control characters must be escaped if they occur as normal data bytes.
Many modern UART implementations support automatic RTS/CTS management internally to simplify application development while maintaining robust transfer reliability.
UART modules remain prevalent in embedded systems due to their simplicity, minimal pin count—usually only TX and RX wires—and broad compatibility across devices ranging from microcontrollers to industrial instruments.
Though external RS-232 ports have largely disappeared from personal computers replaced by USB interfaces since early 2000s designs, internal processors often still embed multiple UART peripherals enabling serial communication channels compatible with legacy standards like RS-232 or RS-485 via level shifting adapters or USB-to-UART bridges offered commercially by companies such as Cypress Semiconductor and FTDI.
Wireless RF modules integrating standard UART interfaces provide transparent serial links over radio frequencies for IoT applications requiring straightforward point-to-point serial connectivity without complex network stacks.
UART’s enduring relevance stems from its straightforward architecture combining configurable parameters—including baud rate selection spanning from low thousands up to several megabits per second—and modular features like FIFO buffers improving throughput without burdening CPU resources excessively. Its well-understood framing format facilitates interoperability across diverse platforms ensuring reliable asynchronous serial communication remains foundational for many embedded communications scenarios today.
[1] https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-tran...
[2] https://www.ezurio.com/resources/blog/an-overview-of-uart-protocol...
[3] https://ebyteiot.com/collections/uart-module?srsltid=AfmBOoqRoGnlT...
[4] https://www.sbg-systems.com/glossary/uart-universal-asynchronous-r...
[5] https://www.analog.com/en/resources/analog-dialogue/articles/uart-...
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